Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-69 Instruction Fault Status Register bit functions (continued)Bits Field Function[10] S Part of the Status field. See bits [3:0] in this table.[9:4] - Reserved. UNP, SBZ.[3:0] Status Indicates the type of exception generated. To determine the data fault, bits [12] and [10] must beused in conjunction with bits [3:0]. The following encodings are listed in priority order, highest first:• bx01100 L1 translation, precise external abort• bx01110 L2 translation, precise external abort• b011100 L1 translation precise parity error• b011110 L2 translation precise parity error• b000101 translation fault, section• b000111 translation fault, page• b000011 access flag fault, section• b000110 access flag fault, page• b001001 domain fault, section• b001011 domain fault, page• b001101 permission fault, section• b001111 permission fault, page• bx01000 precise external abort, nontranslation• b011001 precise parity error• b000010 debug event.Any unused encoding not listed is reserved.Where x represents bit [12] in the encoding, bit [12] can be either:0 = AXI Decode error caused the abort, reset value1 = AXI Slave error caused the abort.NoteWhen the SCR EA bit is set to 1, see c1, Secure Configuration Register on page 3-69,the processor writes to the Secure Instruction Fault Status Register on a Monitor entrycaused by an external abort.To access the Instruction Fault Status Register, read or write CP15 with:MRC p15, 0, , c5, c0, 1 ; Read Instruction Fault Status RegisterMCR p15, 0, , c5, c0, 1 ; Write Instruction Fault Status Register3-86 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E