Cortex-A8 R2P2.pdf - ARM Information Center

Clock, Reset, and Power ControlREFCLK(PLL input)nPORESET8 cycles minimumPRESETn8 cycles minimumATRESETn8 cycles minimumARESETnARESETNEONn16 cycles minimum16 cycles minimumPCLK and ATCLKCLKWhen nPORESET is asserted, CLK must beclamped LOW for a minimum of 2 REFCLK cyclesFigure 10-6 Power-on reset timingFigure 10-6 shows three critical aspects:1. At the beginning of power-on reset, CLK must be held LOW for a minimum ofthe equivalent of two REFCLK clock cycles to place components within theprocessor in a safe state.2. The nPORESET, PRESETn, and ATRESETn resets must be held for eightCLK cycles. This ensures that reset has propagated to all locations within theprocessor.3. The ARESETn and ARESETNEONn resets must be held for an additional eightCLK cycles following the release of nPORESET and PRESETn to enable thosedomains to exit reset safely.Note• The PCLK and ATCLK domains must also be reset during a power-on resetsequence to ensure that the interfaces between those domains and the CLKdomain are reset properly.PRESETn and ATRESETn must be deasserted simultaneously with or after thedeassertion of nPORESET.10-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E