Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorBits Field FunctionTable 3-23 Memory Model Feature Register 2 bit functions (continued)[11:8] Harvard L1 cachemaintenancerange operations[7:4] Harvard L1backgroundprefetch cacherange operations[3:0] Harvard L1foregroundprefetch cacherange operationsIndicates support for cache maintenance range operations, Harvard architecture:0x0 = no support in processor.Indicates support for background prefetch cache range operations, Harvard architecture:0x0 = no support in processor.Indicates support for foreground prefetch cache range operations, Harvard architecture:0x0 = no support in processor.Table 3-24 shows the results of attempted access for each mode.Table 3-24 Results of access to Memory Model Feature Register 2 aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteData Undefined Data Undefined Undefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessorinstruction is executed.To access the Memory Model Feature Register 2, read CP15 with:MRC p15, 0, , c0, c1, 6 ; Read Memory Model Feature Register 23.2.14 c0, Memory Model Feature Register 3The purpose of the Memory Model Feature Register 3 is to provide information aboutthe memory model, memory management, cache support, and TLB operations of theprocessor.The Memory Model Feature Register 3 is:• a read-only register common to the Secure and Nonsecure states• accessible in privileged modes only.Figure 3-10 on page 3-42 shows the bit arrangement of the Memory Model FeatureRegister 3.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-41