Cortex-A8 R2P2.pdf - ARM Information Center

Debugf. 1 indicates that PRSR[1] is set to 1.Accesses to ETM and CTI registersSimilarly to the restrictions on accesses to debug registers as described in Power downpermission on page 12-14, the APB interface can restrict accesses to the ETM and CTIregisters based on the occurrence of power-down events.Table 12-8 shows the behavior of APB interface accesses to ETM and CTI registerswith relation to power-down event.Table 12-8 ETM and CTI registers access with relation to power-down eventConditionsRegistersDBGPWRDWNREQ OS Lock OSLSR OSLAR OSSRR Other a Management b1 X c OK d UNP e UNP ERR f OK0 g 0 OK OK UNP OK OK0 1 h OK OK OK ERR OKa. This column indicates registers in the address range of 0x000 through 0xF00 except for OSLSR, OSLAR,OSSRR, and PRSR registers.b. This column indicates registers in the address range of 0xF04 through 0xFFC.c. X indicates a Don’t care condition. The outcome does not depend on this condition.d. OK indicates that the access succeeds.e. UNP indicates that the access has Unpredictable results; reads return an Unpredictable value.f. ERR indicates a PSLVERR error response; written value is ignored and reads return an Unpredictable value.g. The DBGPWRDWNREQ signal is LOW, indicating the processor is powered up.h. 1 indicates that OSLSR[1] is set to 1.NoteThe OS Lock, OSLSR, OSLAR, OSSRR, and PRSR registers described in this sectionare all part of the ETM programmer’s model. Do not confuse these registers with thedebug registers of the same name.12-16 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E