Cortex-A8 R2P2.pdf - ARM Information Center

Embedded Trace MacrocellTable 14-11 shows how the bit values correspond with the ITMISCIN Registerfunctions. The value of these fields depend on the signals on the input pins when theregister is read.Bits Field FunctionTable 14-11 ITMISCIN Register bit functions[31:5] - Reserved, RAZ[4] DBGACK Returns the value of the DBGACK input[3:0] EXTIN Returns the value of the EXTIN[3:0] inputsITTRIGGER RegisterThe ITTRIGGER Register, trigger request, at offset 0xEE8, is write-only. This registercontrols the signal outputs when bit [0] of the Integration Mode Control Register is setto 1. Figure 14-8 shows the bit arrangement of the ITTRIGGER Register.31 1 0ReservedTRIGGERFigure 14-8 ITTRIGGER Register formatTable 14-12 shows how the bit values correspond with the ITTRIGGER Registerfunctions.Table 14-12 ITTRIGGER Register bit functionsBits Field Function[31:1] - Reserved, SBZ[0] TRIGGER Drives the TRIGGER outputITATBDATA0 RegisterThe ITATBDATA0 Register, ATB data 0, at offset 0xEEC, is write-only. This registercontrols signal outputs when bit [0] of the Integration Mode Control Register is set to1. Figure 14-9 on page 14-20 shows the bit assignment of the ITATBDATA0 Register.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 14-19