Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-72 shows the results of attempted access for each mode.Table 3-72 Results of access to the Instruction Fault Address Register aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteSecure data Secure data NonsecuredataNonsecuredataUndefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when thecoprocessor instruction is executed.To access the IFAR, read or write CP15 with:MRC p15, 0, , c6, c0, 2 ; Read Instruction Fault Address RegisterMCR p15, 0, , c6, c0, 2 ; Write Instruction Fault Address RegisterA write to this register sets the IFAR to the value of the data written. This is useful fora debugger to restore the value of the IFAR.3.2.40 c7, cache operationsThe purpose of c7 is to manage the associated cache levels. The maintenance operationsare formed into two management groups:• Set and way:— clean— invalidate— clean and invalidate.• MVA:— clean— invalidate— clean and invalidate.In addition, the maintenance operations use the following definitions:Point of coherencyThe time when the imposition of any more cache becomes transparent forinstruction, data, and translation table walk accesses to that address byany processor in the system.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-89