Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-32 shows the results of attempted access for each mode.Table 3-32 Results of access to Instruction Set Attributes Register 2 aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteData Undefined Data Undefined Undefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessorinstruction is executed.To access the Instruction Set Attributes Register 2, read CP15 with:MRC p15, 0, , c0, c2, 2 ; Read Instruction Set Attributes Register 23.2.18 c0, Instruction Set Attributes Register 3The purpose of the Instruction Set Attributes Register 3 is to provide information aboutthe instruction set that the processor supports beyond the basic set.The Instruction Set Attributes Register 3 is:• a read-only registers common to the Secure and Nonsecure states• accessible in privileged modes only.Figure 3-14 shows the bit arrangement of Instruction Set Attributes Register 3.31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0Thumb TableNOPSWI SIMD Saturatecopy branchinstructionsinstructions instructions instructionsinstructions instructionsThumb2 executable environment extensionSynchronization primitive instructionsFigure 3-14 Instruction Set Attributes Register 3 format3-48 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E