Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-77 shows how the bit values correspond with the Cache Operation functions forMVA format operations.Bits Field FunctionTable 3-77 Functional bits of c7 for MVA[31:6] Modified virtual address Specifies address to invalidate, clean, or prefetch[5:0] - Reserved, SBZSBZThe value supplied Should-Be-Zero. The value 0x00000000 must be written to theregister.VA to PA translation operationsThe purpose of the VA to PA translation operations, nonsecure operations, is to providea secure means to determine address translation between the Secure and Nonsecurestates. VA to PA translations operate through:• PA Register• VA to PA translation in the current Secure or Nonsecure state on page 3-97• VA to PA translation in the other Secure or Nonsecure state on page 3-97.PA RegisterThe purpose of the Physical Address Register (PAR) is to hold:• the Physical Address (PA) after a successful translation• the source of the abort for an unsuccessful translation.Table 3-78 on page 3-94 shows the purpose of the bits of the PAR for successfultranslations and Table 3-79 on page 3-96 shows the purpose of the bits of the PAR forunsuccessful translations.The PAR is:• a read/write register banked in Secure and Nonsecure states• accessible in privileged modes only.Figure 3-34 on page 3-94 shows the bit arrangement of the PAR for successfultranslations.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-93