Cortex-A8 R2P2.pdf - ARM Information Center

Programmer’s ModelImprecise data abortsThe state of the system presented to the abort exception handler for an imprecise dataabort can be the state for an instruction after the instruction that caused the abort. As aresult, it is not often possible to restart the processor from the point at which theexception occurred.Data aborts that occur because of watchpoints are precise.2.15.7 Imprecise data abort mask in the CPSR/SPSRAn imprecise data abort caused, for example, by an external error on a write that hasbeen held in a write buffer, is asynchronous to the execution of the causing instruction.The imprecise data abort can occur many cycles after the instruction that caused thememory access has retired. For this reason, the imprecise data abort can occur at a timethat the processor is in Abort mode because of a precise data abort, or can have live statein Abort mode, but be handling an interrupt.To avoid the loss of the Abort mode state (r14_abt and SPSR_abt) in these cases, thatleads the processor to enter an unrecoverable state, the system must hold the existenceof a pending imprecise data abort until a time when the Abort mode can safely beentered.A mask is included in the CPSR to indicate that an imprecise data abort can be accepted.This bit is referred to as the A bit. The imprecise data abort causes a data abort to betaken when imprecise data aborts are not masked. When imprecise data aborts aremasked, then the implementation is responsible for holding the presence of a pendingimprecise data abort until the mask is cleared to 0 and the abort is taken. The A bit is setto 1 automatically on entry into Abort Mode, IRQ, and FIQ Modes, and on Reset. Seethe ARM Architecture Reference Manual for more information.NoteYou cannot change the CPSR A bit in the Nonsecure state if the SCR bit [5] is reset. Youcan change the SPSR A bit in the Nonsecure state but this does not update the CPSR ifthe SCR bit [5] does not permit it.2.15.8 Software interrupt instructionYou can use the Supervisor Call (SVC) instruction to enter Supervisor mode, usually torequest a particular supervisor function. The SVC handler reads the opcode to extractthe SVC function number. A SVC handler returns by executing the followinginstruction, irrespective of the processor operating state:MOVS PC, R14_svc2-40 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E