Cortex-A8 R2P2.pdf - ARM Information Center

Instruction Cycle Timing16.2 Instruction-specific scheduling for ARM instructionsThe tables in this section provide information to determine the best-case instructionscheduling for a sequence of instructions. The information includes:• when source registers are required• when destination registers are available• which register, such as Rn or Rm, is meant for each source or destination• the minimum number of cycles required for each instruction• any additional instruction issue requirements or restrictions.When a source register is required or a destination register is available depends on theavailability of forwarding paths to route the required data from the correct source to thecorrect destination.Special considerations and caveats concerning the instruction tables include:• Source requirements are always given for the first cycle in a multi-cycleinstruction.• Destination available is always given with respect to the last cycle in a dataprocessing multi-cycle instruction. This rule does not apply to load/store multipleinstructions.• Multiply instructions issue to pipeline 0 only.• Flags from the CPSR Register are updated internally in the E2 stage.• [Rd] as a source register indicates the destination register is required as a sourceif the instruction is conditional.• {} on a source register indicate the register is required only if the instructionincludes an accumulator operand.• () on a destination register indicate the destination is required only if writeback isenabled.• [] on a load instruction destination register indicate that the destination register isoptional depending on the size of the data transferred.16.2.1 Example of how to read ARM instruction tablesThis section provides examples of how to read ARM instruction tables described in thechapter. See the ARM Architecture Reference Manual for assembly syntax ofinstructions.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 16-3