Cortex-A8 R2P2.pdf - ARM Information Center

Memory Management Unit6.1 About the MMUThe MMU works with the L1 and L2 memory system to translate virtual addresses tophysical addresses. It also controls accesses to and from external memory. See the ARMArchitecture Reference Manual for a full architectural description of the MMU.The processor implements the ARMv7-A MMU enhanced with Security Extensionsfeatures to provide address translation and access permission checks. The MMUcontrols table walk hardware that accesses translation tables in main memory. TheMMU enables fine-grained memory system control through a set of virtual-to-physicaladdress mappings and memory attributes held in instruction and data TLBs.The MMU features include the following:• full support for Virtual Memory System Architecture version 7 (VMSAv7)• separate, fully-associative, 32-entry data and instruction TLBs• support for 32 lockable entries using the lock-by-entry model• TLB entries that support 4KB, 64KB, 1MB, and 16MB pages• 16 domains• global and application-specific identifiers to prevent context switch TLB flushes• extended permissions check capability• round-robin replacement policy• CP15 TLB preloading instructions to enable locking of TLB entries.6-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E