Cortex-A8 R2P2.pdf - ARM Information Center

System Control Coprocessor31 1 0ReservedENFigure 3-45 User Enable Register formatTable 3-100 shows how the bit values correspond with the USEREN Register functions.Table 3-100 User Enable Register bit functionsBitsFieldFunction[31:1] - Reserved. RAZ, SBZP[0] EN User mode enableTable 3-101 shows the results of attempted access for each mode.Table 3-101 Results of access to the User Enable RegisterSecure privileged Nonsecure privileged Secure User Nonsecure UserEN Read Write Read Write Read Write Read Write0Data Data Data Data DataUndefinedexceptionDataUndefinedexception1 Data Data Data Data Data UndefinedexceptionDataUndefinedexceptionTo access the USEREN Register, read or write CP15 with:MRC p15, 0, , c9, c14, 0 ; Read USEREN RegisterMCR p15, 0, , c9, c14, 0 ; Write USEREN Register3.2.52 c9, Interrupt Enable Set RegisterThe purpose of the INTerrupt ENable Set (INTENS) Register is to determine if any ofthe Performance Monitor Count Registers, PMCNT0-PMCNT3 and CCNT, generate aninterrupt on overflow.The INTENS Register is:• a read/write register common to Secure and Nonsecure states• accessible in privileged mode only.3-118 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E