Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-46 Control Register bit functions (continued)Bits Field Access Function[13] V bit Banked Determines the location of exception vectors, see c12, Secure or Nonsecure VectorBase Address Register on page 3-153. The primary input VINITHI defines the resetvalue of the V bit:0 = Normal exception vectors selected, reset value. The Vector Base Address Registersdetermine the address range.1 = High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C.[12] I bit Banked Determines if instructions can be cached in any instruction cache at any cache level:0= instruction caching disabled at all levels, reset value1 = instruction caching enabled.[11] Z bit Banked Enables program flow prediction:0 = program flow prediction disabled, reset value1 = program flow prediction enabled.[10:7] - - Reserved. RAZ, SBZP.[6:3] - - Reserved. Read-As-One (RAO), Should-Be-One or Preserved (SBOP).[2] C bit Banked Determines if data can be cached in a data or unified cache at any cache level:0 = datacaching disabled at all levels, reset value1 = data caching enabled.[1] A bit Banked Enables strict alignment of data to detect alignment faults in data accesses:0 = strict alignment fault checking disabled, reset value1 = strict alignment fault checking enabled.[0] M bit Banked Enables the MMU:0 = MMU disabled, reset value1 = MMU enabled.Attempts to read or write the Control Register from secure or nonsecure User modesresult in an Undefined Instruction exception.Attempts to write to this register in secure privileged mode when CP15SDISABLE isHIGH result in an Undefined Instruction exception, see Security Extensions writeaccess disable on page 2-46.3-60 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E