Cortex-A8 R2P2.pdf - ARM Information Center

Design for Test11.1.2 MBIST registersTable 11-1 shows the MBIST registers. See Figure 11-7 on page 11-20 for informationabout the timing of an MBIST instruction load.Table 11-1 MBIST register summaryRegister Access ReferenceL1 MBIST Instruction Register W See L1 MBIST Instruction RegisterL2 MBIST Instruction Register W See L2 MBIST Instruction Register on page 11-7L1 and L2 MBIST GO-NOGOInstruction RegistersWSee L1 and L2 MBIST GO-NOGO InstructionRegisters on page 11-13L1 MBIST Datalog Register R See L1 MBIST Datalog Register on page 11-14L2 MBIST Datalog Register R See L2 MBIST Datalog Register on page 11-16L1 MBIST Instruction RegisterFigure 11-1 shows the fields of the L1 MBIST Instruction Register.L1_config[14:0]Inpttn[5:0]L1_array_sel[22:0]L1_ADDR_SCRAMBLE[183:0]rtfailbitmapdseed[3:0]HVAB_rows[2:0]GHB_rows[2:0]BTB_rows[2:0]TAG_rows[2:0]DATA_rows[2:0]Figure 11-1 L1 MBIST Instruction Register bit assignmentsARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 11-3