Cortex-A8 R2P2.pdf - ARM Information Center

NEON and VFP Programmer’s Model13.5 Modes of operationTo accommodate a variety of applications, the VFP coprocessor provides four modes ofoperation:• Full-compliance mode• Flush-to-zero mode• Default NaN mode• RunFast mode.13.5.1 Full-compliance modeWhen the VFP coprocessor is in full-compliance mode, all operations are processedaccording to the IEEE 754 standard in hardware.13.5.2 Flush-to-zero modeSetting the FZ bit, FPSCR[24], enables flush-to-zero mode and increases performanceon very small inputs and results. In flush-to-zero mode, the VFP coprocessor treats allsubnormal input operands of arithmetic CDP operations as zeros in the operation.Exceptions that result from a zero operand are signaled appropriately. FABS, FNEG,and FCPY are not considered arithmetic CDP operations and are not affected byflush-to-zero mode. A result that is tiny, as described in the IEEE 754 standard, for thedestination precision is smaller in magnitude than the minimum normal value beforerounding and is replaced with a zero. The IDC flag, FPSCR[7], indicates when an inputflush occurs. The UFC flag, FPSCR[3], indicates when a result flush occurs.13.5.3 Default NaN modeSetting the DN bit, FPSCR[25], enables default NaN mode. In default NaN mode, theresult of any operation that involves an input NaN or generated a NaN result returns thedefault NaN. Propagation of the fraction bits is maintained only by FABS, FNEG, andFCPY operations, all other CDP operations ignore any information in the fraction bitsof an input NaN.13.5.4 RunFast modeRunFast mode is the combination of the following conditions:• the VFP coprocessor is in flush-to-zero mode• the VFP coprocessor is in default NaN mode• all exception enable bits are cleared to 0.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 13-21