Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorYou can configure the TLB Lockdown Registers to exclude a range of entries from theround-robin allocation scheme. You must use the TLB Lockdown Registers with theTLB preload operation. See c10, TLB preload operation on page 3-130 for moreinformation.The TLB Lockdown Registers are:• read/write registers common to Secure and Nonsecure states• accessible in privileged modes only.Figure 3-50 shows the bit arrangement of the Data and Instruction TLB LockdownRegisters.31 27 26 22 21 1 0Base Victim Reserved PBits Field FunctionFigure 3-50 TLB Lockdown Register formatTable 3-110 shows how the bit values correspond with the Data and Instruction TLBLockdown Register functions.For the Data or Instruction TLB Lockdown Register:Table 3-110 TLB Lockdown Register bit functions[31:27] Base Defines the offset from TLB entry 0 for which entries 0 to base - 1 are locked assuming P equals 1during a hardware translation table walk.[26:22] Victim Specifies the entry where the next hardware translation table walk can place a TLB entry. The resetvalue is 0. Each hardware translation table walk increments the value of the Victim field.[21:1] - Reserved. UNP, SBZP.[0] P Determines if TLB entries allocated by subsequent translation table walks are not invalidated by theInvalidate TLB unlocked entries operation:0 = allocated TLB entries are invalidated, reset value1 = allocated TLB entries are not invalidated.• The TLB lockdown behavior depends on the TL bit, see c1, Nonsecure AccessControl Register on page 3-73. If the TL bit is not set to 1, the lockdown entriesare reserved for the Secure state.• The TLB Lockdown Register must be used with the TLB preload operation. Seec10, TLB preload operation on page 3-130.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-129