Cortex-A8 R2P2.pdf - ARM Information Center

DebugBits Field FunctionTable 12-14 Debug Status and Control Register bit functions (continued)[26] DTRTXfull_l The latched DTRTXfull flag. This flag is read in one of the following ways:• using CP14 instruction• using the DSCR memory address• using the OSSRR memory address.CP14 instruction returns an Unpredictable value for this bit.DSCR memory address returns the same value as DTRTXfull.OSSRR memory address returns the latched DTRTXfull value, that is, the value ofDTRTXfull that the processor captured on the last DSCR memory address read.If a read to the DTRTX APB address succeeds, DTRTXfull_l is cleared to 0.[25] StickypipelineadvanceSticky pipeline advance bit. This bit enables the debugger to detect whether the processor isidle. In some situations, this might mean that the system bus port is deadlock. This bit is setto 1 every time the processor pipeline retires one instruction. A write to DRCR[3] clears thisbit to 0. See Debug Run Control Register on page 12-36.0 = no instruction has completed execution since the last time this bit was cleared, reset value1 = an instruction has completed execution since the last time this bit was cleared.[24] InstrCompl_l The latched InstrCompl flag. This flag is read in one of the following ways:• using CP14 instruction• using the DSCR memory address• using the OSSRR memory address.CP14 instruction returns an Unpredictable value for this bit.DSCR memory address returns the same value as InstrCompl.OSSRR memory address returns the latched InstrCompl value, that is, the value ofInstrCompl that the processor captured on the last DSCR memory address read.If a write to the ITR APB address succeeds while in Stall or Nonblocking mode,InstrCompl_l and InstrCompl are cleared to 0.If a write to the DTRRX APB address or a read to the DTRTX APB address succeeds whilein Fast mode, InstrCompl_l and InstrCompl are cleared to 0.InstrCompl is the instruction complete bit. This internal flag determines whether theprocessor has completed execution of an instruction issued through the APB interface.0 = the processor is currently executing an instruction fetched from the ITR Register, resetvalue1 = the processor is not currently executing an instruction fetched from the ITR Register.[23:22] - Reserved. UNP, SBZP.12-24 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E