Cortex-A8 R2P2.pdf - ARM Information Center

DebugBits Field FunctionTable 12-14 Debug Status and Control Register bit functions (continued)[15] Monitordebug-mode[14] Haltingdebug-mode[13] Executeinstructionenable[12] CP14 useraccess disable[11] InterruptdisableThe Monitor debug-mode enable bit. This is a read/write bit.0 = Monitor debug-mode disabled, reset value1 = Monitor debug-mode enabled.If Halting debug-mode is enabled, bit [14] is set to 1, then the processor is in Haltingdebug-mode regardless of the value of bit [15]. If the external interface input DBGEN isLOW, DSCR[15] reads as 0. If DBGEN is HIGH, then the read value reverts to theprogrammed value.The Halting debug-mode enable bit. This is a read/write bit.0 = Halting debug-mode disabled, reset value1 = Halting debug-mode enabled.If the external interface input DBGEN is LOW, DSCR[14] reads as 0. If DBGEN is HIGH,then the read value reverts to the programmed value.Execute ARM instruction enable bit. This is a read/write bit.0 = disabled, reset value1 = enabled.If this bit is set to 1 and an ITR write succeeds, the processor fetches an instruction from theITR for execution. If this bit is set to 1 when the processor is not in debug state, the behaviorof the processor is Unpredictable.CP14 debug user access disable control bit. This is a read/write bit.0 = CP14 debug user access enable, reset value1 = CP14 debug user access disable.If this bit is set to 1 and a User mode process tries to access any CP14 debug registers, theUndefined Instruction exception is taken.Interrupts disable bit. This is a read/write bit.0 = interrupts enabled, reset value1 = interrupts disabled.If this bit is set to 1, the IRQ and FIQ input signals are disabled. The external debugger canset this bit to 1 before it executes code in normal state as part of the debugging process. Ifthis bit is set to 1, an interrupt does not take control of the program flow. For example, thedebugger might use this bit to execute an OS service routine to bring a page from disk intomemory. It might be undesirable to service any interrupt during the routine execution.[10] DbgAck Debug Acknowledge bit. This is a read/write bit. If this bit is set to 1, both the DBGACKand DBGTRIGGER output signals are forced HIGH, regardless of the processor state. Theexternal debugger can use this bit if it wants the system to behave as if the processor is indebug state. Some systems rely on DBGACK to determine whether the application ordebugger generates the data accesses. The reset value is 0.12-26 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E