Cortex-A8 R2P2.pdf - ARM Information Center

DebugUpdating CPSR bitsIf the debugger writes to the CPSR a value so that it sets the CPSR[4:0] bits to aprocessor mode where invasive debug is not permitted, this update of the CPSR[4:0]bits is ignored. Similarly, if invasive debug is not permitted for privilege modes in thecurrent security state, writes to the CPSR privileged bits are ignored.Table 12-55 shows which updates are permitted in debug state:Table 12-55 Permitted updates to the CPSR in debug stateModeSecure state a orMonitor modeDBGEN & SPIDENModify CPSR[4:0]to Monitor modeUpdate privilegedCPSR bits bUser Yes 0 Update ignored Update ignoredPrivileged Yes 0 Permitted PermittedAny No 0 Update ignored PermittedAny X 1 Permitted Permitteda. The processor is in secure state when CP15 SCR[0] nonsecure bit is set to 0.b. This column excludes the case where the debugger attempts to change CPSR[4:0] to Monitor mode, that is, itonly includes updates of the A, I, or F bits, or the CPSR[4:0] bits to a mode other than Monitor.Writing to the CPSR SCRWhile in debug state, if the debugger forces the processor to execute a CP15 MCRinstruction to write to the CP15 Secure Configuration Register (SCR), it is onlypermitted to execute if either of these conditions is true:• the processor is in a secure privileged mode including Monitor mode• the processor is in secure User mode, and both DBGEN and SPIDEN areasserted.Note• Writes to the SCR while in nonsecure state are not permitted even if both DBGENand SPIDEN are asserted, except if the processor is in Monitor mode because itis considered to be a secure privileged mode regardless of the value of the SCR[0]NS bit.• The processor treats attempts to write to the SCR when they are not permitted asUndefined instruction exceptions. See Exceptions in debug state on page 12-84for details of how the processor behaves when Undefined instruction exceptionsoccur while in debug state.12-82 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E