Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-19 shows how the bit values correspond with the Memory Model FeatureRegister 0 functions.Table 3-19 Memory Model Feature Register 0 bit functionsBits Field Function[31:28] - Reserved, RAZ.[27:24] FCSE Indicates support for fast context switch memory mappings:0x1 = Processor supports FCSE.[23:20] Auxiliary ControlRegisterIndicates support for Auxiliary Control Register:0x1 = Processor supports the Auxiliary Control Register.[19:16] TCM Indicates support for TCM and associated DMA:0x0 = Processor does not support TCM and DMA.[15:12] Outer shareable Indicates support for outer shareable attribute:0x0 = Processor does not support this model.[11:8] Cache coherence Indicates support for cache coherency maintenance:0x0 = Processor does not support this model.[7:4] PMSA Indicates support for Physical Memory System Architecture (PMSA):0x0 = Processor does not support PMSA.[3:0] VMSA Indicates support for Virtual Memory System Architecture (VMSA).0x3 = Processor supports:• VMSA v7 including cache and TLB type register• Extensions to ARMv6.Table 3-20 shows the results of attempted access for each mode.Table 3-20 Results of access to Memory Model Feature Register 0 aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteData Undefined Data Undefined Undefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessorinstruction is executed.To access the Memory Model Feature Register 0, read CP15 with:MRC p15, 0, , c0, c1, 4 ; Read Memory Model Feature Register 03-36 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E