Cortex-A8 R2P2.pdf - ARM Information Center

DebugTable 12-26 Watchpoint Control Registers bit functions (continued)Bits Field Function[4:3] L/S Load/store access. The watchpoint can be conditioned to the type of access being done:b00 = reservedb01 = load, load exclusive, or swapb10 = store, store exclusive or swapb11 = either.SWP and SWPB trigger a watchpoint on b01, b10, or b11. A load exclusive instruction triggersa watchpoint on b01 or b11. A store exclusive instruction triggers a watchpoint on b10 or b11only if it passes the local monitor within the processor. a[2:1] S Privileged access control. The watchpoint can be conditioned to the privilege of the accessbeing done:b00 = reservedb01 = privileged, match if the processor does a privileged access to memoryb10 = User, match only on nonprivileged accessesb11 = either, match all accesses.NoteFor all cases, the match refers to the privilege of the access, not the mode of the processor.[0] W Watchpoint enable:0 = watchpoint disabled, reset value1 = watchpoint enabled.a. A store exclusive that fails the local monitor does not cause a translation table walk, MMU fault, or watchpoint, seeStore-exclusive instruction on page 8-12.12.4.17 Operating System Lock Access RegisterThe OSLAR is a write-only register that locks the debug registers so that the APBinterface returns a slave-generated error response for accesses to locked registers. Thisis useful for the OS to interrupt the debug session cleanly when it wants to save the stateof the debug registers.Figure 12-14 shows the bit arrangement of the OS Lock Access Register.31 0OS lock accessFigure 12-14 OS Lock Access Register format12-46 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E