Cortex-A8 R2P2.pdf - ARM Information Center

Instruction Cycle Timing16.3 Dual-instruction issue restrictionsCalculating likely instruction pairings is part of the hand calculation process required todetermine the timing for a sequence of instructions. The processor issues a pair ofinstructions unless it encounters an issue restriction. Table 16-12 shows the mostcommon issue restriction cases. This table contains references to pipeline 0 and pipeline1. The first instruction always issues in pipeline 0 and the second instruction, if present,issues in pipeline 1. If only one instruction issues, it always issues in pipeline 0.Restrictiontype Description Example Cycle RestrictionTable 16-12 Dual-issue restrictionsLoad/storeresourcehazardThere is only one LS pipeline.Only one LS instruction can beissued per cycle. It can be inpipeline 0 or pipeline 1LDR r5, [r6]STR r7, [r8]MOV r9, r10122Wait for LS unitDual issue possibleMultiplyresourcehazardThere is only one multiplypipeline, and it is only availablein pipeline 0.ADD r1, r2, r3MUL r4, r5, r6MUL r7, r8, r9123Wait for pipeline 0Wait for multiply unitBranchresourcehazardThere can be only one branch percycle. It can be in pipeline 0 orpipeline 1. A branch is anyinstruction that changes the PC.BX r1BEQ 0x1000ADD r1, r2, r3122Wait for branchDual issue possibleDataoutputhazardInstructions with the samedestination cannot be issued inthe same cycle. This can happenwith conditional code.MOVEQ r1, r2MOVNE r1, r3LDR r5, [r6]122Wait because of output dependencyDual issue possibleDatasourcehazardInstructions cannot be issued iftheir data is not available. See thescheduling tables for sourcerequirements and stages results.ADD r1, r2, r3ADD r4, r1, r6LDR r7, [r4]124Wait for r1Wait two cycles for r4Multi-cycleinstructionMulti-cycle instructions mustissue in pipeline 0 and can onlydual issue in their last iteration.MOV r1, r2LDM r3, {r4-r7}LDM (cycle 2)LDM (cycle 3)ADD r8, r9, r1012344Wait for pipeline 0, transfer r4Transfer r5, r6Transfer r7Dual issue possible on last transferARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 16-13