Cortex-A8 R2P2.pdf - ARM Information Center

Instruction Cycle Timing16.4 Other pipeline-dependent latenciesThis section describes a variety of other factors that can affect the timing of a codesequence. For the most part, these factors cannot be accurately predicted on a case bycase basis, but can be accounted for statistically if determining the overall timing for alarger section of code.16.4.1 Cycle penalty for instruction flow changeWhenever a control flow change occurs in the processor that the prefetch unit has notpredicted, the pipeline must be flushed. This results in a cycle stall equal in number tothe length of the integer pipeline. This branch mispredict penalty is 13 cycles. SeeChapter 5 Program Flow Prediction for details on program execution prediction.16.4.2 Memory system effects on instruction timingsBecause the processor is a statically scheduled design, any stall from the memorysystem can result in the minimum of a 8-cycle delay. This 8-cycle delay minimum isbalanced with the minimum number of possible cycles to receive data from the L2 cachein the case of an L1 load miss. Table 16-13 gives the most common cases that can resultin an instruction replay because of a memory system stall.Table 16-13 Memory system effects on instruction timingsReplayeventDelayDescriptionLoad datamiss8 cycles 1. A load instruction misses in the L1 data cache.2. A request is then made to the L2 data cache.3. If a miss also occurs in the L2 data cache, then a second replay occurs. Thenumber of stall cycles depends on the external system memory timing. Theminimum time required to receive the critical word for an L2 cache miss isapproximately 25 cycles, but can be much longer because of L3 memorylatencies.16-14 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E