Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-97 Values for predefined events (continued)Value0x050x060x070x080x090x0A0x0B0x0C0x0D0x0EDescriptionData read or write operation that causes a TLB refill at the lowest level of TLB. Each data read or writeoperation that causes a translation table walk or an access to another level of TLB caching is counted. CP15TLB maintenance operations do not count as events. This counter increments for speculative data accessesand for data accesses that are explicitly made by instructions.Data read architecturally executed. This counter increments for every instruction that explicitly read data,including SWP. This counter only increments for instructions that are unconditional or that pass theircondition codes.Data write architecturally executed. The counter increments for every instruction that explicitly wrote data,including SWP. This counter only increments for instructions that are unconditional or that pass theircondition codes.Instruction architecturally executed. This counter counts for all instructions, including conditionalinstructions that fail their condition codes.Exception taken. This counts for each exception taken.Exception return architecturally executed. This includes:• RFE {!}• MOVS PC (and other similar data processing instructions)• LDM Rn{!}, This counter only increments for instructions that are unconditional or that pass their condition codes.Instruction that writes to the Context ID Register architecturally executed. This counter only increments forinstructions that are unconditional or that pass their condition codes.Software change of PC, except by an exception, architecturally executed. This counter only increments forinstructions that are unconditional or that pass their condition codes.Immediate branch architecturally executed, taken or not taken. This includes B{L}, BLX, CB{N}Z, HB{L},and HBLP. This counter counts for all immediate branch instructions that are architecturally executed,including conditional instructions that fail their condition codes.Procedure return, other than exception returns, architecturally executed. This includes:• BX R14• MOV PC, LR• POP {..., PC}• LDR PC, [R13], #offset• LDMIA R9!, {...,PC}• LDR PC, [R9], #offsetThis counter only increments for instructions that are unconditional or that pass their condition codes.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-113