Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-3 Summary of CP15 registers and operations (continued)CRn Op1 CRm Op2Register oroperationSecurity state Reset value PageNSSc12 0 c0 0 Secure orNonsecure VectorBase Address1 Monitor VectorBase AddressR/W R/W, B, X 0x00000000 page 3-153NA R/W, X 0x00000000 page 3-1552-7 Undefined - - - -c1 0 Interrupt Status RO RO 0x00000000 f page 3-1571-7 Undefined - - - -c2-15 0-7 Undefined - - - -1-7 c0-15 0-7 Undefined - - - -c13 0 c0 0 FCSE PID R/W R/W, B, X 0x00000000 page 3-1581 Context ID R/W R/W, B Unpredictable page 3-1612 User read/writeThread and ProcessIDR/W R/W, B Unpredictable page 3-1623 User read-onlyThread and ProcessIDR/W,ROR/W, RO, Unpredictable page 3-162B g4 Privileged onlyThread and ProcessIDR/W R/W, B Unpredictable page 3-1625-7 Undefined - - - -c1-c15 0-7 Undefined - - - -1-7 c0-c15 0-7 Undefined - - - -c14 0-7 c0-c15 0-7 Undefined - - - -c15 0 c0 0 D-L1 Data 0RegisterNA R/W Unpredictable page 3-1633-20 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E