Cortex-A8 R2P2.pdf - ARM Information Center

Design for TestTable 11-8 Selecting L2 data array latency with L2DLat[3:0] (continued)L2DLat[3:0]Wait statesb1010 11b1011 12b1100 13b1101 14b1110 15b1111 16L2TLat[1:0]Use the L2TLat[1:0] field to select the read and write latency of the L2 tag array asTable 11-9 shows. Reset sets the L2TLat[1:0] field, selecting four wait states.Table 11-9 Selecting L2 tag array latency with L2TLat[1:0]L2TLat[1:0]Wait statesb00 2b01 2b10 3b11 4L2Rows[11:0]The four 3-bit fields in the L2Rows[11:0] field control the number of rows in the data,parity, tag, and valid RAMs. Table 11-10 shows the fields that control each of the fourRAMs.Table 11-10 Selecting the L2 RAMs with L2Rows[11:0]Bit range Reset value Function[11:9] b100 Selects number of data RAM rows11-10 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E