Cortex-A8 R2P2.pdf - ARM Information Center

List of FiguresFigure 10-13 Retention power domains ..................................................................................... 10-27Figure 11-1 L1 MBIST Instruction Register bit assignments ...................................................... 11-3Figure 11-2 L2 MBIST Instruction Register bit assignments ...................................................... 11-8Figure 11-3 L1 and L2 MBIST GO-NOGO Instruction Registers bit assignments ................... 11-13Figure 11-4 L1 MBIST GO-NOGO Instruction Register example with two patterns ................ 11-14Figure 11-5 L1 MBIST Datalog Register bit assignments ........................................................ 11-15Figure 11-6 L2 MBIST Datalog Register bit assignments ........................................................ 11-16Figure 11-7 Timing of MBIST instruction load .......................................................................... 11-20Figure 11-8 Timing of MBIST custom GO-NOGO instruction load .......................................... 11-21Figure 11-9 Timing of MBIST at-speed execution .................................................................... 11-22Figure 11-10 Timing of MBIST end-of-test datalog retrieval ...................................................... 11-23Figure 11-11 Timing of MBIST start of bitmap datalog retrieval ................................................. 11-23Figure 11-12 Timing of MBIST end of bitmap datalog retrieval .................................................. 11-24Figure 11-13 Physical array after pass 1 of CKBD .................................................................... 11-27Figure 11-14 Physical array after pass 1 of COLBAR ................................................................ 11-28Figure 11-15 Physical array after pass 1 of ROWBAR .............................................................. 11-29Figure 11-16 Row 1 column 2 state during pass 2 of RWXMARCH .......................................... 11-30Figure 11-17 Row 1 column 2 state during pass 2 of RWYMARCH .......................................... 11-30Figure 11-18 Row 1 column 2 state during pass 2 of RWRXMARCH ....................................... 11-31Figure 11-19 Row 1 column 2 state during pass 2 of RWRYMARCH ....................................... 11-31Figure 11-20 Row 1 column 2 state during pass 2 of XMARCHC ............................................. 11-32Figure 11-21 Row 1 column 2 state during pass 2 of YMARCHC ............................................. 11-33Figure 11-22 XADDRBAR array accessing and data ................................................................. 11-33Figure 11-23 YADDRBAR array accessing and data ................................................................. 11-34Figure 11-24 WRITEBANG ........................................................................................................ 11-35Figure 11-25 READBANG .......................................................................................................... 11-35Figure 11-26 Input wrapper boundary register cell control logic ................................................ 11-38Figure 11-27 Output wrapper boundary register cell control logic ............................................. 11-38Figure 11-28 IEEE 1500-compliant input wrapper boundary register cell .................................. 11-39Figure 11-29 Reset handling ...................................................................................................... 11-40Figure 11-30 Safe shift RAM signal ........................................................................................... 11-40Figure 12-1 Typical debug system ............................................................................................. 12-2Figure 12-2 Debug ID Register format ..................................................................................... 12-18Figure 12-3 Debug ROM Address Register format .................................................................. 12-20Figure 12-4 Debug Self Address Offset Register format .......................................................... 12-21Figure 12-5 Debug Status and Control Register format ........................................................... 12-22Figure 12-6 DTR Register format ............................................................................................. 12-30Figure 12-7 Vector Catch Register format ............................................................................... 12-31Figure 12-8 Event Catch Register format ................................................................................. 12-34Figure 12-9 Debug State Cache Control Register format ........................................................ 12-35Figure 12-10 ITR format ............................................................................................................. 12-35Figure 12-11 Debug Run Control Register format ..................................................................... 12-36Figure 12-12 Breakpoint Control Registers format ..................................................................... 12-38Figure 12-13 Watchpoint Control Registers format .................................................................... 12-43Figure 12-14 OS Lock Access Register format .......................................................................... 12-46Figure 12-15 OS Lock Status Register format ........................................................................... 12-47Figure 12-16 OS Save and Restore Register format ................................................................. 12-48xxiv Copyright © 2006-2008 ARM Limited. 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