Cortex-A8 R2P2.pdf - ARM Information Center

NEON and VFP Programmer’s ModelComparisonsComparison results modify condition code flags in the FPSCR Register. The FMSTATinstruction transfers the current condition code flags in the FPSCR Register to the CPSRRegister. See the ARM Architecture Reference Manual for more information. Thecondition code flags used are chosen so that subsequent conditional execution of ARMinstructions can test the predicates defined in the IEEE 754 standard.The VFP coprocessor handles all comparisons of numeric and reserved values inhardware, generating the appropriate condition code depending on whether the result isless than, equal to, or greater than.The VFP coprocessor supports:Compare operationsThe compare operations are FCMPS, FCMPZS, FCMPD, and FCMPZD.A compare instruction involving a QNaN produces an unordered result.An SNaN produces an unordered result and generates an InvalidOperation exception.Compare with exception operationsThe compare with exception operations are FCMPES, FCMPEZS, FCMPED, andFCMPEZD.A compare with exception operation involving either an SNaN or aQNaN produces an unordered result and generates an Invalid Operationexception.UnderflowIn the generation of Underflow exceptions, the before rounding form of tininess and theinexact result form of loss of accuracy as described in the IEEE 754 standard, are used.In flush-to-zero mode, results that are tiny before rounding, as described in the IEEE754 standard, are flushed to a zero, and the UFC flag, FPSCR[3], is set to 1. See theARM Architecture Reference Manual for information on flush-to-zero mode.When the VFP coprocessor is not in flush-to-zero mode, operations are performed onsubnormal operands. If the operation does not produce a tiny result, it returns thecomputed result, and the UFC flag, FPSCR[3], is not set to 1. The IXC flag, FPSCR[4],is set to 1 if the operation is inexact. If the operation produces a tiny result, the result isa subnormal or zero value, and the UFC flag, FPSCR[3], is set to 1.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 13-25