Cortex-A8 R2P2.pdf - ARM Information Center

Contents7.8 Parity detection ......................................................................................... 7-13Chapter 8Chapter 9Chapter 10Chapter 11Chapter 12Chapter 13Level 2 Memory System8.1 About the L2 memory system ..................................................................... 8-28.2 Cache organization ..................................................................................... 8-38.3 Enabling and disabling the L2 cache controller ........................................... 8-58.4 L2 PLE ........................................................................................................ 8-68.5 Synchronization primitives ........................................................................ 8-118.6 Locked access .......................................................................................... 8-138.7 Parity and error correction code ................................................................ 8-14External Memory Interface9.1 About the external memory interface .......................................................... 9-29.2 AXI control signals in the processor ............................................................ 9-49.3 AXI instruction transactions ........................................................................ 9-79.4 AXI data read/write transactions ................................................................. 9-8Clock, Reset, and Power Control10.1 Clock domains .......................................................................................... 10-210.2 Reset domains .......................................................................................... 10-510.3 Power control .......................................................................................... 10-10Design for Test11.1 MBIST ....................................................................................................... 11-211.2 ATPG test features ................................................................................. 11-37Debug12.1 Debug systems ......................................................................................... 12-212.2 About the debug unit ................................................................................. 12-412.3 Debug register interface ............................................................................ 12-712.4 Debug register descriptions .................................................................... 12-1712.5 Management registers ............................................................................ 12-5412.6 Debug events .......................................................................................... 12-7012.7 Debug exception ..................................................................................... 12-7412.8 Debug state ............................................................................................. 12-7812.9 Cache debug ........................................................................................... 12-8712.10 External debug interface ......................................................................... 12-8912.11 Using the debug functionality .................................................................. 12-9412.12 Debugging systems with energy management capabilities .................. 12-116NEON and VFP Programmer’s Model13.1 About the NEON and VFP programmer’s model ...................................... 13-213.2 General-purpose registers ........................................................................ 13-413.3 Short vectors ............................................................................................. 13-613.4 System registers ..................................................................................... 13-1213.5 Modes of operation ................................................................................. 13-21ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. vii