Cortex-A8 R2P2.pdf - ARM Information Center

Clock, Reset, and Power Control10.3 Power controlBoth the clocks and resets in the processor play key roles in the power management ofthe processor, enabling islands to be powered down or powered up in a controlledmanner. They also provide many key control mechanisms to manage dynamic power.This section describes:• Dynamic power management• Static or leakage power management on page 10-14• Debugging the processor while powered down on page 10-23• L1 data and L2 cache power domains on page 10-25• Special note on reset during power transition on page 10-29.10.3.1 Dynamic power managementThe processor has many different dynamic power management facilities. The mostcommon form of dynamic power management is control of the clock network within theprocessor.The processor has three levels of clock gating to manage dynamic power. The levelscorrespond to the following functions:Level 1Level 2Level 3This is architectural gating, also known as Wait-For-Interrupt (WFI), orthe CLKSTOPREQ and CLKSTOPACK signals on the Cortex-A8processor.This is major function gating, such as NEON, ETM, or integer coregating.This is state element gating, such as local clock gating.The processor contains all hardware necessary for architecture, unit, and local clockgating. No external hardware is required to clock gate the processor.Wait-For-Interrupt architectureExecuting a Wait-For-Interrupt instruction puts the processor into a low-power stateuntil one of the following occurs:• an IRQ or FIQ interrupt• a halting debug event when the DBGNOCLKSTOP signal is HIGH.See Halting debug event on page 12-71 for information on halting debug events.10-10 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E