Cortex-A8 R2P2.pdf - ARM Information Center

Design for Testprocessorinput portsWEXTESTWINTESTWSESingle WSE logicprocessorinput portsCAPTUREWRTESTMODESERIALTESTSHIFTWRHold control logic10SEin01To inputWBR cellscapture_inputs_nshift_inputsFigure 11-26 Input wrapper boundary register cell control logicFigure 11-27 shows the RTL logic for a set of output WBR cells.processorinput portsWEXTESTWINTESTWSESingle WSE logicprocessorinput portsCAPTUREWRTESTMODESERIALTESTSHIFTWRHold control logic10SEin01To outputWBR cellscapture_outputs_nshift_outputsFigure 11-27 Output wrapper boundary register cell control logicThe hold control logic in Figure 11-26 and Figure 11-27 has capture and shift signalsthat enable the WBR cell to hold data during test mode while both these signals aredeasserted. The only difference between the input wrapper and output wrapper cells isthat the WINTEST and WEXTEST connections switch polarity. The type of IEEE1500 compliant-wrapper cell used with this logic is shown in Figure 11-28 onpage 11-39.This utilization provides the benefit of requiring only one external wrapper scan enableand preventing unknown states from being output from the WBR cells during patternswith multiple capture cycles. If you use a standard multiplexed-scan flip-flop in the11-38 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E