Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorSecurity Extensions write access disableThe processor supports a primary input pin, CP15SDISABLE, to disable write accessto the CP15 registers.When the CP15SDISABLE input is set to 1, any attempt to write to the secure versionof the banked register, NS-bit is 0, or any non-banked register, NS-state is 0 results inan Undefined Instruction exception.Changes in the pin on an instruction boundary occur as quickly as practically possibleafter a change to this pin. Software must perform a IMB after a change to this pin hasoccurred on the boundary of the macros to ensure that its effects are recognized onfollowing instructions.At reset, it is expected that this pin is set to logic 0 by the SoC hardware. Control of thispin is expected to remain within the SoC chip that implements the processor.Table 3-2 shows the CP15 registers affected by the primary input pin,CP15SDISABLE.Table 3-2 CP15 registers affected by CP15SDISABLERegisterInstructionControl Register MCR p15, 0, , c1, c0, 0Translation Table Base 0 MCR p15, 0, , c2, c0, 0Translation Table Control Register MCR p15, 0, , c2, c0, 2Domain Access Control MCR p15, 0, , c3, c0, 0Primary Region Remap MCR p15, 0, , c10, c2, 0Normal Memory Region Remap MCR p15, 0, , c10, c2, 1Vector Base MCR p15, 0, , c12, c0, 0Monitor Base MCR p15, 0, , c12, c0, 1FCSE MCR p15, 0, , c13, c0, 0Array operations MCR p15, 0, , c15, c0-15, 0-7MRC p15, 0, , c15, c0-15, 0-73-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E