Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-126 PLE Control Register bit functions (continued)Bits Field Function[28] IE Indicates that the PLE channel must assert an interrupt on an error.The interrupt is deasserted from this source, when the channel is set to idle with a clear operation. Seec11, PLE enable commands on page 3-143 for more information.NoteIf the U bit is set to 1, then an interrupt on error occurs regardless of the state of the IE bit. See c11,PLE User Accessibility Register on page 3-139 for information on the U bit.0 = no interrupt on error1 = interrupt on error.[27] - Reserved. UNP, SBZP.[26] UM Indicates that the permission checks are based on the PLE in User or privileged mode. The UM bit isprovided so that the privileged mode process can emulate a User mode. See Table 3-127 onpage 3-146 for more details on the UM bit:0 = transfer is a privileged transfer1 = transfer is a User mode transfer.[25:3] - Reserved. UNP, SBZP.[2:0] WY Indicates the selected L2 cache way for filling data. This is used in conjunction with the L2 CacheLockdown Register:b000 = way 0b001 = way 1b010 = way 2b011 = way 3b100 = way 4b101 = way 5b110 = way 6b111 = way 7.Access in the Nonsecure state depends on the PLE bit, see c1, Nonsecure AccessControl Register on page 3-73. The processor can access this register in User mode ifthe U bit for the currently selected channel is set to 1, see c11, PLE User AccessibilityRegister on page 3-139.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-145