Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-134 shows how the bit values correspond with the PLE Context ID Registerfunctions.Bits Field FunctionTable 3-134 PLE Context ID Register bit functions[31:8] PROCID Extends the ASID to form the process ID and identifies the current process[7:0] ASID Holds the ASID of the current process and identifies the current ASIDAccess in the Nonsecure state depends on the PLE bit, see c1, Nonsecure AccessControl Register on page 3-73. Table 3-135 shows the results of attempted access foreach mode.Table 3-135 Results of access to the PLE Context ID Register aSecure privileged Nonsecure privileged Secure User Nonsecure UserPLE bit Read Write Read Write Read Write Read Write0 Data Data Undefined Undefined Undefined Undefined Undefined Undefined1 Data Data Data Data Undefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessorinstruction is executed.To access the PLE Context ID Register in a privileged mode, set the PLE ChannelNumber Register to the appropriate PLE channel and read or write CP15 with:MRC p15, 0, , c11, c15, 0 ; Read PLE Context ID RegisterMCR p15, 0, , c11, c15, 0 ; Write PLE Context ID Register3.2.68 c12, Secure or Nonsecure Vector Base Address RegisterThe purpose of the Secure or Nonsecure Vector Base Address Register is to hold thebase address for exception vectors in the Secure and Nonsecure states. See Exceptionson page 2-35 for more information.The Secure or Nonsecure Vector Base Address Register is:• a read/write register banked in Secure and Nonsecure states• accessible in privileged modes only.Figure 3-61 on page 3-154 shows the bit arrangement of the Secure or NonsecureVector Base Address Register.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-153