Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTo access the Memory Region Remap Registers read or write CP15 with:MRC p15, 0, , c10, c2, 0 ; Read Primary Region Remap RegisterMCR p15, 0, , c10, c2, 0 ; Write Primary Region Remap RegisterMRC p15, 0, , c10, c2, 1 ; Read Normal Memory Remap RegisterMCR p15, 0, , c10, c2, 1 ; Write Normal Memory Remap RegisterMemory remap occurs in two stages:1. The processor uses the Primary Region Remap Register to remap the primarymemory type, normal, device, or strongly ordered, and the shareable attribute.2. For memory regions that the Primary Region Remap Register defines as Normalmemory, the processor uses the Normal Memory Remap Register to remap theinner and outer cacheable attributes.The behavior of the Memory Region Remap Registers depends on the TEX Remap bit,see c1, Control Register on page 3-58. If the TEX Remap bit is set to 1, the entries inthe Memory Region Remap Registers remap each possible value of the TEX[0], C andB bits in the translation tables. You can therefore set your own definitions for thesevalues. If the TEX Remap bit is cleared to 0, the Memory Region Remap Registers arenot used and no memory remapping takes place. See MMU software-accessibleregisters on page 6-8 for more information.The Memory Region Remap Registers are expected to remain static during normaloperation. When you write to the Memory Region Remap Registers, you mustinvalidate the TLB and perform an IMB operation before you can rely on the newwritten values. You must also stop the PLE if it is running.NoteFor security reasons, you cannot remap the NS bit.3.2.59 c11, PLE Identification and Status RegistersThe purpose of the PLE Identification and Status Registers is to define:• the PLE channels that are physically implemented on the particular device• the current status of the PLE channels.Processes that handle PLE can read this register to determine the physical resourcesimplemented and their availability.The PLE Identification and Status Register is:• four read-only registers common to Secure and Nonsecure states• accessible only in privileged modes.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-137