Cortex-A8 R2P2.pdf - ARM Information Center

AC Characteristics17.4 APB interface and miscellaneous debug signalsTable 17-4 shows the setup and hold times for:• the APB interface• the miscellaneous debug signals.PCLK is the clock for the APB interface and some miscellaneous debug signals, andCLK is the clock for all other miscellaneous debug signals.Table 17-4 Timing parameters of APB interface and miscellaneous debug signalsSignal Clock Setup parameterPercent ofclock periodHold parameterCOMMRX a CLK T ovcommrx 30% T ohcommrxCOMMTX a CLK T ovcommtx 30% T ohcommtxDBGACK CLK T ovdbgack 30% T ohdbgackDBGNOCLKSTOP CLK T isdbgnoclkstop 30% T ihdbgnoclkstopDBGROMADDR[31:12] b CLK T isdbgromaddr 30% T ihdbgromaddrDBGROMADDRV b CLK T isdbgromaddrv 30% T ihdbgromaddrvDBGSELFADDR[31:12] b CLK T isdbgselfaddr 30% T ihdbgselfaddrDBGSELFADDRV b CLK T isdbgselfaddrv 30% T ihdbgselfaddrvEDBGRQ a PCLK - - -DBGEN PCLK - - -DBGOSLOCKINIT b PCLK T isdbgoslockinit 30% T ihdbgoslockinitDBGNOPWRDWN a PCLK T ovdbgnopwrdwn 30% T ohdbgnopwrdwnDBGPWRDWNREQ a PCLK - - -ETMPWRDWNREQ a,c PCLK - - -DBGPWRDWNACK PCLK T ovdbgpwrdwnack 30% T ohdbgpwrdwnackETMPWRDWNACK c PCLK T ovetmpwrdwnack 30% T ohetmpwrdwnackPRESETn a,d PCLK - - -PCLKEN PCLK T ispclken 30% T ihpclkenARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 17-7