Cortex-A8 R2P2.pdf - ARM Information Center

Cross Trigger InterfaceBits Field Function[31:4] - Reserved. RAZ, SBZ.Table 15-10 shows how the bit values correspond with these registers.Table 15-10 CTI Channel to Trigger Enable Registers bit functions[3:0] TRIGOUTEN Enables a channel event for the corresponding channel to generate an CTITRIGOUT output:0 = the channel input CTICHIN from the CTM is not routed to the CTITRIGOUT output1 = the channel input CTICHIN from the CTM is routed to the CTITRIGOUT output.There is one bit of the register for each of the four channels. For example, enabling bit [0] inRegister CTIOUTEN0, enables CTICHIN[0] to cause a trigger event on theCTITRIGOUT[0] output.15.6.8 CTI Trigger In Status Register, CTITRIGINSTATUSCTITRIGINSTATUS is a read-only register that provides the status of the CTITRIGINinputs.Figure 15-11 shows the bit arrangement of the CTITRIGINSTATUS Register.31 9 80ReservedTRIGINSTATUSBits Field Function[31:9] - Reserved, RAZ.Figure 15-11 CTI Trigger In Status Register formatTable 15-11 shows how the bit values correspond with the CTITRIGINSTATUSRegister functions.Table 15-11 CTI Trigger In Status Register bit functions[8:0] TRIGINSTATUS Displays the status of the CTITRIGIN inputs:0 = CTITRIGIN is inactive1 = CTITRIGIN is active.Because the register provides a view of the raw CTITRIGIN inputs, the reset value isunknown. There is one bit of the register for each trigger input.15-18 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E