Cortex-A8 R2P2.pdf - ARM Information Center

DebugBitsFieldFunctionTable 12-16 shows how the bit values correspond with the WFAR functions.Table 12-16 Watchpoint Fault Address Register bit functions[31:1] - Virtual address of the watchpointed instruction. When a watchpoint occurs in ARM state, the WFARcontains the address of the instruction causing it plus 0x8. When a watchpoint occurs in Thumb state,the address is plus 0x4. The reset value is Unpredictable.[0] - Reserved. UNP, SBZ.12.4.8 Vector Catch RegisterThe processor supports efficient exception vector catching. This is controlled by theread/write Vector Catch Register as Figure 12-7 shows.Nonsecure worldSecure world31 30 29 28 27 26 25 24 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0ReservedFIQIRQReservedData abortPrefetch abortSVCUndefinedFIQIRQReservedData abortPrefetch abortSMCReservedSecure Monitor entryResetUndefinedSVCPrefetch abortData abortReservedIRQFIQFigure 12-7 Vector Catch Register formatIf one of the bits in this register is set to 1 and the corresponding vector is committedfor execution, then the processor either enters debug state or takes a debug exception.Note• Under this model, any kind of prefetch of an exception vector can trigger a vectorcatch, not only the ones caused by exception entries. An explicit branch to anexception vector might generate a vector catch debug event.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-31