Cortex-A8 R2P2.pdf - ARM Information Center

Clock, Reset, and Power Control2. For applications that do retain the L1 data cache or L2 unified cache RAMcontents throughout a core power-down sequence, hardware must control both theL1RSTDISABLE and L2RSTDISABLE signals during reset. When the systemis powering up for the first time, the hardware reset signals, L1RSTDISABLEand L2RSTDISABLE, must be tied LOW to invalidate both the L1 data cacheand L2 unified cache RAM contents using the hardware reset mechanism. Ifeither the L1 data cache or L2 unified cache must retain its data during a resetsequence, then the corresponding hardware reset disable must be tied HIGH.3. If the hardware array reset mechanism is not used, then both theL1RSTDISABLE and L2RSTDISABLE pins must be tied HIGH.Both the L1RSTDISABLE and L2RSTDISABLE pins must be valid at least 16 CLKcycles before and after the deasserting edge of ARESETn and nPORESET.10.2.5 Reset of memory arraysDuring reset of the processor, the following memory arrays are invalidated at reset:• branch prediction arrays (BTB and GHB)• L1 instruction and data TLBs• L1 data cache valid RAM, if L1RSTDISABLE is tied LOW• L2 unified cache valid RAM, if L2RSTDISABLE is tied LOW.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 10-9