Cortex-A8 R2P2.pdf - ARM Information Center

Programmer’s Model2.13 RegistersThe processor has a total of 40 registers:• 33 general-purpose 32-bit registers• seven 32-bit status registers.These registers are not all accessible at the same time. The processor state and mode ofoperation determine which registers are available to the programmer.2.13.1 The state register setIn ARM state, 16 data registers and one or two status registers are accessible at any time.In privileged modes, mode-specific banked registers become available. Figure 2-10 onpage 2-25 shows which registers are available in each mode.Thumb and ThumbEE state give access to the same set of registers as ARM state.However, the 16-bit instructions provide only limited access to some of the registers. Nosuch limitations exist for 32-bit Thumb-2 and ThumbEE instructions.Registers r0 through r13 are general-purpose registers used to hold either data oraddress values.Registers r14 and r15 have the following special functions:Link RegisterRegister r14 is used as the subroutine Link Register (LR).Register r14 receives the return address when the processorexecutes a Branch with Link (BL or BLX) instruction.You can treat r14 as a general-purpose register at all other times.Similarly, the corresponding banked registers r14_mon, r14_svc,r14_irq, r14_fiq, r14_abt, and r14_und hold the return valueswhen the processor receives interrupts and exceptions, or when itexecutes the BL or BLX instructions within interrupt or exceptionroutines.Program Counter Register r15 holds the PC:• in ARM state, this is word-aligned• in Thumb state, this is halfword-aligned• in ThumbEE state, this is halfword-aligned.One of the status registers, the Current Program Status Register (CPSR), containscondition code flags, status bits, and current mode bits.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 2-23