Cortex-A8 R2P2.pdf - ARM Information Center

Clock, Reset, and Power ControlPower cycle the core with L2 cache retaining stateA power down and reset sequence of the processor with the L2 cache retained is asfollows:1. Clean to the point of unification the L1 data cache.2. Save off any TLB state such as locked entries, if required.3. Save off architectural state, if required.4. Assert L2RSTDISABLE to disable L2 hardware reset.5. Reset and power down the processor. See Powering down the integer core powerdomain on page 10-24.6. Power up the processor. See Powering up the integer core and NEON powerdomains on page 10-24.7. Perform a normal software initialization of the L1 instruction and data caches.8. Perform a software read of a memory location to determine that the L2 has validdata and to skip the L2 software invalidation.9. Before enabling the L2 cache or using any CP15 cache-related operations,software must signal the system to release the L2 cache input clamps and receiveconfirmation that the clamps have been released.Power cycle the core with L1 data cache and L2 cache retaining stateA power down and reset sequence of the processor with the L1 data cache and L2 cacheis as follows:1. Save off any TLB state such as locked entries, if required.2. Save off architectural state, if required.3. Assert L1RSTDISABLE and L2RSTDISABLE to inhibit hardware reset of theL1 data cache and L2 cache.4. Reset and power down the processor. See Powering down the integer core powerdomain on page 10-24.5. Power up the processor. See Powering up the integer core and NEON powerdomains on page 10-24.6. Perform a normal software initialization of the L1 instruction cache.10-28 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E