Cortex-A8 R2P2.pdf - ARM Information Center

Introduction1.3.4 Load/storeThe load/store unit encompasses the entire L1 data side memory system and the integerload/store pipeline. This includes:• the L1 data cache• the data side TLB• the integer store buffer• the NEON store buffer• the integer load data alignment and formatting• the integer store data alignment and formatting.The pipeline accepts one load or store per cycle that can be present in either pipeline 0or pipeline 1. This gives the processor flexibility when scheduling load and storeinstructions. See Chapter 7 Level 1 Memory System for more information.1.3.5 L2 cacheThe L2 cache unit includes the L2 cache and the Buffer Interface Unit (BIU). It servicesL1 cache misses from both the instruction fetch unit and the load/store unit. SeeChapter 8 Level 2 Memory System and Chapter 9 External Memory Interface for moreinformation.1.3.6 NEONThe NEON unit includes the full 10-stage NEON pipeline that decodes and executes theAdvanced SIMD media instruction set. The NEON unit includes:• the NEON instruction queue• the NEON load data queue• two pipelines of NEON decode logic• three execution pipelines for Advanced SIMD integer instructions• two execution pipelines for Advanced SIMD floating-point instructions• one execution pipeline for Advanced SIMD and VFP load/store instructions• the VFP engine for full execution of the VFPv3 data-processing instruction set.See Chapter 13 NEON and VFP Programmer’s Model for programming information onthe NEON and VFP coprocessor.1.3.7 ETMThe ETM unit is a non-intrusive trace macrocell that filters and compresses aninstruction and data trace for use in system debugging and system profiling.1-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E