Cortex-A8 R2P2.pdf - ARM Information Center

List of TablesTable 12-1 Access to CP14 debug registers ............................................................................ 12-7Table 12-2 CP14 debug registers summary ............................................................................. 12-8Table 12-3 Debug memory-mapped registers .......................................................................... 12-9Table 12-4 Processor reset effect on debug and ETM logic ................................................... 12-12Table 12-5 APB interface access with relation to software lock ............................................. 12-14Table 12-6 Debug registers access with relation to power-down event .................................. 12-15Table 12-7 Power management registers access with relation to power-down event ............ 12-15Table 12-8 ETM and CTI registers access with relation to power-down event ....................... 12-16Table 12-9 Terms used in register descriptions ...................................................................... 12-17Table 12-10 CP14 debug registers ........................................................................................... 12-17Table 12-11 Debug ID Register bit functions ............................................................................ 12-19Table 12-12 Debug ROM Address Register bit functions ......................................................... 12-20Table 12-13 Debug Self Address Offset Register bit functions ................................................. 12-21Table 12-14 Debug Status and Control Register bit functions .................................................. 12-23Table 12-15 Data Transfer Register bit functions ..................................................................... 12-30Table 12-16 Watchpoint Fault Address Register bit functions .................................................. 12-31Table 12-17 Vector Catch Register bit functions ...................................................................... 12-32Table 12-18 Event Catch Register bit functions ........................................................................ 12-34Table 12-19 Debug State Cache Control Register bit functions ............................................... 12-35Table 12-20 Instruction Transfer Register bit functions ............................................................ 12-36Table 12-21 Debug Run Control Register bit functions ............................................................ 12-37Table 12-22 Breakpoint Value Registers bit functions .............................................................. 12-38Table 12-23 Breakpoint Control Registers bit functions ............................................................ 12-39Table 12-24 Meaning of BVR bits [22:20] ................................................................................. 12-41Table 12-25 Watchpoint Value Registers bit functions ............................................................. 12-42Table 12-26 Watchpoint Control Registers bit functions ........................................................... 12-44Table 12-27 OS Lock Access Register bit functions ................................................................. 12-47Table 12-28 OS Lock Status Register bit functions .................................................................. 12-48Table 12-29 OS Save and Restore Register bit functions ........................................................ 12-49Table 12-30 PRCR bit functions ............................................................................................... 12-51Table 12-31 PRSR bit functions ................................................................................................ 12-52Table 12-32 Management registers .......................................................................................... 12-54Table 12-33 Processor Identifier Registers ............................................................................... 12-55Table 12-34 Integration Internal Output Control Register bit functions ..................................... 12-57Table 12-35 Integration External Output Control Register bit functions .................................... 12-59Table 12-36 Integration Input Status Register bit functions ...................................................... 12-60Table 12-37 Integration Mode Control Register bit functions .................................................... 12-61Table 12-38 Claim Tag Set Register bit functions .................................................................... 12-62Table 12-39 Claim Tag Clear Register bit functions ................................................................. 12-62Table 12-40 Lock Access Register bit functions ....................................................................... 12-63Table 12-41 Lock Status Register bit functions ........................................................................ 12-64Table 12-42 Authentication Status Register bit functions ......................................................... 12-65Table 12-43 Device Type Register bit functions ....................................................................... 12-66Table 12-44 Peripheral Identification Registers ........................................................................ 12-66Table 12-45 Fields in the Peripheral Identification Registers .................................................... 12-67Table 12-46 Peripheral ID Register 0 bit functions ................................................................... 12-67Table 12-47 Peripheral ID Register 1 bit functions ................................................................... 12-68xvi Copyright © 2006-2008 ARM Limited. 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