Cortex-A8 R2P2.pdf - ARM Information Center

Debugmultiprocessor trace and debug architecture. This ROM holds information about all thecomponents in the debug bus. You can configure the address read in this register usingDBGROMADDR[31:12] and DBGROMADDRV inputs. DBGROMADDRV mustbe tied off to 1 if DBGROMADDR[31:12] is tied off to a valid value.The Debug ROM Address Register is:• in CP14 c0• a read-only register• accessible in User and privileged modes.Figure 12-3 shows the bit arrangement of the Debug ROM Address Register.31 12 11 2 1 0Debug bus ROM physical addressReservedValid bitsBits Field FunctionFigure 12-3 Debug ROM Address Register formatTable 12-12 shows how the bit values correspond with the Debug ROM AddressRegister functions.Table 12-12 Debug ROM Address Register bit functions[31:12] Debug bus ROMphysical addressIndicates bits [31:12] of the debug bus ROM physical address.[11:2] - Reserved. UNP, SBZP.[1:0] Valid bits Reads b11 if DBGROMADDRV is set to 1, reads b00 otherwise. DBGROMADDRVmust be set to 1 if DBGROMADDR[31:12] is set to a valid value.To access the Debug ROM Address Register, read CP14 c0 with:MRC p14, 0, , c1, c0, 0 ; Read Debug ROM Address Register12.4.4 CP14 c0, Debug Self Address Offset RegisterThe Debug Self Address Offset Register is a read-only register that returns a 20-bitoffset value from the Debug ROM Address Register to the physical address of theprocessor debug registers. The address read from this register depends on theDBGSELFADDR[31:12] and DBGSELFADDRV inputs. DBGSELFADDRV mustbe tied off to 1 if DBGSELFADDR[31:12] is tied off to a valid value.12-20 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E