Cortex-A8 R2P2.pdf - ARM Information Center

System Control Coprocessor31 29 28N+1 N6 5 0Reserved Address ReservedAddressAddressTagarrayFigure 3-86 L2 tag array read operation formatFigure 3-87 shows the bit arrangement of the L2 tag array write operation.31 N+1 N 8 7 5 4 2 1 0L2 Data 0 registerTagReservedDataDataReserved31 29 28N+1 N6 5 0ReservedAddressReservedAddressAddressWrite dataTagarrayTo write one entry to the L2 tag array, for example:Figure 3-87 L2 tag array write operation formatLDR R0, =0x000020D1;MCR p15, 0, R0, c15, c8, 0;LDR R1, =0x400000C0;MCR p15, 0, R1, c15, c8, 2;Move R0 to L2 Data 0 RegisterWrite L2 Data 0 Register to L2 tag RAMTo read one entry from the L2 tag array, for example:LDR R1, =0x400000C0;MCR p15, 0, R1, c15, c9, 2;MRC p15, 0, R2, c15, c8, 0;Read L2 tag RAM into L2 Data 0 RegisterMove L2 Data 0 Register to R23.2.84 c15, L2 data array operationsThe purpose of the L2 data array operations is to:• read the L2 data array contents and write into the system debug data registers• write into the system debug data registers and copy into the L2 data array.3-184 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E