Cortex-A8 R2P2.pdf - ARM Information Center

DebugCoprocessor instructionsThe rules for executing coprocessor instructions other than CP14 and CP15 while indebug state are the same as in normal state. CP14 debug instructions are alwayspermitted while in debug state regardless of the debug permissions, processor mode,and security state.NoteNondebug CP14 instructions behave as CP15 instructions while in debug state.For CP15 instructions, the processor behaves as follows:• If the debugger is permitted to execute an MSR instruction to change the CPSR[4:0]bits to a privileged mode, then the debugger is also permitted to access privilegedCP15 registers. In this situation, the debugger is not required to switch theprocessor into a privileged mode before executing a privileged CP15 instruction.• If the processor is in nonsecure state and is permitted to change to Monitor mode,it must do so before issuing CP15 instructions that must be executed in a secureprivileged mode. In this case, the processor is not automatically granted secureprivileged permissions.• If the debugger tries to execute a CP15 instruction that is not permitted, theprocessor generates an Undefined Instruction exception. See Exceptions in debugstate on page 12-84 for information on how the processor behaves whenUndefined instruction exceptions occur while in debug state.Table 12-56 shows the CP14 and CP15 instruction execution rules.Table 12-56 Accesses to CP15 and CP14 registers in debug stateModeSCR[0]DBGEN &SPIDENAccessto CP14registersAccess tobanked CP15registersAccess torestricted accessCP15 registersAccess toconfigurableaccess CP15registersUser 0 0 Permitted Undefined Undefined UndefinedUser 0 1 Permitted Secure Permitted PermittedMonitor 0 X Permitted Secure Permitted PermittedMonitor 1 X Permitted Nonsecure Permitted PermittedPxM a 0 X Permitted Secure Permitted PermittedUser or PxM 1 X Permitted Nonsecure Undefined As configuredARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-83