Cortex-A8 R2P2.pdf - ARM Information Center

External Memory InterfaceTable 9-6 AXI address channel for data transactions - excluding load/store multiples (continued)Transfer NA BW BC a NoT TSSAO[3:0]AxA[31:0]AxLN[3:0]AxS[2:0]AxB[1:0]AxLK[1:0]NoncacheableloaddoublewordNo 64 QW 2 1st - [31:2]00 0 32-bit Incr Normal2nd - [31:4]0000 0 32-bit Incr NormalDW 2 1st - [31:2]00 0 32-bit Incr Normal2nd - [31:3]000 0 32-bit Incr Normal128 QW 2 1st - [31:2]00 0 32-bit Incr Normal2nd - [31:4]0000 0 32-bit Incr NormalDW 2 1st - [31:2]00 0 32-bit Incr Normal2nd - [31:3]000 0 32-bit Incr NormalStronglyordered, ordevice loaddoublewordNo 64 QW 2 1st - [31:2]00 0 32-bit Incr Normal2nd - [31:4]0000 0 32-bit Incr NormalDW 2 1st - [31:2]00 0 32-bit Incr Normal2nd - [31:3]000 0 32-bit Incr Normal128 QW 2 1st - [31:2]00 0 32-bit Incr Normal2nd - [31:4]0000 0 32-bit Incr NormalDW 2 1st - [31:2]00 0 32-bit Incr Normal2nd - [31:3]000 0 32-bit Incr NormalNoncacheable,or stronglyordered, ordevice storebyteNoncacheable,or stronglyordered, ordevice storehalfwordYes 64 N/A 1 - - [31:0] 0 8-bit Incr Normal128 N/A 1 - - [31:0] 0 8-bit Incr NormalYes 64 N/A 1 - - [31:1]0 0 16-bit Incr Normal128 N/A 1 - - [31:1]0 0 16-bit Incr NormalARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 9-11