Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorFor the processor, the L1 and L2 cache are configurable at implementation time.Therefore, the set and way fields are unique to the configured cache sizes. Table 3-75shows the values of A, L, and S for L1 cache sizes, and Table 3-76 shows the values ofA, L, and S for L2 cache sizes.Table 3-75 Values of A, L, and S for L1 cache sizesL1 A L S Way Set Level16KB 2 6 6 [31:30] [11:6] [3:1]32KB 2 6 7 [31:30] [12:6] [3:1]Table 3-76 shows the values of A, L, and S for L2 cache sizes and the resultant bit rangefor Way, Set, and Level. See Table 3-74 on page 3-91 and Figure 3-32 on page 3-91.Table 3-76 Values of A, L, and S for L2 cache sizesL2 A L S Way Set Level0KB 3 6 0 [31:29] - [3:1]128KB 3 6 8 [31:29] [13:6] [3:1]256KB 3 6 9 [31:29] [14:6] [3:1]512KB 3 6 10 [31:29] [15:6] [3:1]1024KB 3 6 11 [31:29] [16:6] [3:1]See c0, Cache Type Register on page 3-26 for more information on cache sizes.MVAFigure 3-33 shows the MVA format for invalidate, clean, and prefetch operations.31 6 5 0Modified virtual addressReservedFigure 3-33 c7 format for MVA3-92 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E