Cortex-A8 R2P2.pdf - ARM Information Center

Embedded Trace MacrocellActual ComponentID register fields ID3 Register ID2 Register ID1 Register ID0 Register7 0 7 0 7 0 7 0Conceptual 32-bit component ID31 24 23 16 15 8 7 0Component IDFigure 14-5 Mapping between the Component ID Registers and the component ID valueTable 14-7 shows the bit field definitions of the Component Identification Registers.This register structure is defined in the ETM Architecture Specification.Table 14-7 Component Identification Registers bit functionsRegisterRegisteroffsetBitrangeValueFunctionComponentID3 0xFFC [31:8] - Unused, RAZ[7:0] 0xB1 Component identifier, bits [31:24]ComponentID2 0xFF8 [31:8] - Unused, RAZ[7:0] 0x05 Component identifier, bits [23:16]ComponentID1 0xFF4 [31:8] - Unused, RAZ[7:4] 0x9 Component class; component identifier, bits [15:12][3:0] 0x0 Component identifier, bits [11:8]ComponentID0 0xFF0 [31:8] - Unused, RAZ[7:0] 0x0D Component identifier, bits [7:0]14.4.6 Integration Test RegistersThe following sections describe the Integration Test Registers. To access these registersyou must first set bit [0] of the Integration Mode Control Register to 1.• You can use the write-only Integration Test Registers to set the outputs of someof the ETM signals. Table 14-8 on page 14-17 lists the signals that can becontrolled in this way.• You can use the read-only Integration Test Registers to read the state of some ofthe ETM input signals. Table 14-9 on page 14-17 lists the signals that can be readin this way.14-16 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E