Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorBits Field FunctionTable 3-66 shows how the bit values correspond with the Domain Access ControlRegister functions.Table 3-66 Domain Access Control Register bit functions- D a The fields D15-D0 in the register define the access permissions for each one of the 16 domains. Thesedomains can be either sections, large pages, or small pages of memory:b00 = No access. Any access generates a domain fault.b01 = Client. Accesses are checked against the access permission bits in the TLB entry.b10 = Reserved. Any access generates a domain fault.b11 = Manager. Accesses are not checked against the access permission bits in the TLB entry, so apermission fault cannot be generated. Attempting to execute code in a page that has the TLB eXecuteNever (XN) attribute set does not generate an abort.a. n is the Domain number in the range between 0 and 15Attempts to write to this register in secure privileged mode when CP15SDISABLE isHIGH result in an Undefined Instruction exception, see Security Extensions writeaccess disable on page 2-46.Table 3-67 shows the results of attempted access for each mode.Table 3-67 Results of access to the Domain Access Control Register aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteSecuredataSecuredataNonsecuredataNonsecuredataUndefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when thecoprocessor instruction is executed.To access the Domain Access Control Register, read or write CP15 with:MRC p15, 0, , c3, c0, 0 ; Read Domain Access Control RegisterMCR p15, 0, , c3, c0, 0 ; Write Domain Access Control Register3.2.35 c5, Data Fault Status RegisterThe purpose of the Data Fault Status Register (DFSR) is to hold the source of the lastdata fault.3-82 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E